(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to combine feed-forward and feed-backward methods and a high-polymer based hole profile in order to achieve a constant and reducible hole bottom.
(2) Description of the Prior Art
The formation of semiconductor devices comprises the formation of numerous device features such as the creation of patterned and etched layer of semiconductor material, the creation of patterns in a deposited layer of semiconductor material, the creation of regions of conductivity in either the surface of a silicon substrate or in deposited layers of semiconductor material, the formation of conductive interconnect traces, and the like. As examples of these processes can be cited the formation of patterned and etched layers of gate oxide and thereover a layer of polysilicon for the formation of gate electrodes, the creation of Lightly Doped Diffusion and source/drain regions in the surface of a substrate self-aligned with created layers of gate electrode material and the doping of a layer of polysilicon in order to provide the desired conductivity to this layer of polysilicon for use as for instance a layer of gate electrode material. These and other processes of creating device features are subject to Critical Dimension (or minimum width) control, which is a reflection of the accuracy that is achieved by the creative process that may comprise using photolithographic technology with exposure masks or reticles, layers of photoresist for the exposure of surfaces that need to be etched, etc. For reasons of wafer and device throughput and device performance, the variation of the Critical Dimension must be within strict and well-established limits. Any deviation from this limit leads to product rework or product rejection, both courses of action adding to the final product cost and must therefore be avoided wherever possible.
In many cases, deviation from the allowable CD limit is determined at the level of photoresist development. Where product that is being created is detected to not meet the CD limit at the photoresist development stage, most commonly the developed layer of photoresist is removed and the cycle of product creation is restarted with a new layer of photoresist. This is an approach that in again leads to increased product cost and in addition does not provide for prevention of a repetition of the experienced problem, since no feedback mechanism is applied to perhaps correct the exposure of the layer of photoresist prior to the re-development of the layer of photoresist.
The invention specifically addresses the creation of openings, which may be via openings or contact openings. A conventional method of creating such openings applies and develops a layer of photoresist, which has been coated over the surface of a layer of semiconductor material, and measures the CD of the opening created in the layer of photoresist. For product that passes this measurement, the process continues with the etching of the layer of semiconductor material in which the opening is to be created, after which the developed layer of photoresist is removed. Accumulated impurities, such as remnants of photoresist or polymers, are then removed after which the CD of the created opening is measured. Most openings are created through a layer of insulation or dielectric, as a final operation the surface of the layer of dielectric may be polished in order to assure good planarity, which is of particular importance in order to maintain good planarity for thereover created layers and device features.
The conventional method as highlighted above does not make use of any in-process feedback loops that dynamically, real-time correct for errors that are present in the cycle of creating openings, as confirmed by failure to meet CD specifications. The invention addresses this concern.
U.S. Pat. No. 5,926,690 (Toprac) shows a run-to-run control process for controlling Critical Dimension. It can reduce the impact from After Development Inspection (ADI) DC, but not the post CMP thickness.
U.S. Pat. No. 6,225,134 (Meisner) teaches a method for linewidth control.
U.S. Pat. No. 6,309,976 B1 (Lin et al.) shows a CD control method including an After Development Inspection (ADI).
U.S. Pat. No. 6,235,440 B1 (Tao et al.) shows a gate CD control method including an ADI.
U.S. Pat. No. 6,161,054 (Rosenthal et al.) teaches a cell control method.